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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7841 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com octal 14-bit, parallel input, voltage-output dac functional block diagram dac reg a input reg a dac e ad7841 db13 db0 wr cs a0 a1 a2 ldac rr rr r r r r r r r r r r r r dac reg b input reg b dac reg c input reg c dac reg d input reg d dac reg e input reg e dac reg f input reg f dac reg g input reg g dac reg h input reg h 14 dac d dac c dac f dac b dac a dac g dac h v cc v ss v dd v ref (+) ab v ref (? ab dutgnd cd dutgnd ab v out a v out b v out c v out d v out e v out f v out g v out h dutgnd gh dutgnd ef v ref (? cdef v ref (+) cdef v ref (? gh v ref (+) gh gnd clr address decode 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 features eight 14-bit dacs in one package voltage outputs offset adjust for each dac pair reference range of 5 v maximum output voltage range of 10 v 15 v 10% operation clear function to user-defined voltage 44-lead mqfp package applications automatic test equipment process control general purpose instrumentation general description the ad7841 contains eight 14-bit dacs on one monolithic chip. it has output voltages with a full-scale range of 10 v from reference voltages of 5 v. the ad7841 accepts 14-bit parallel loaded data from the exter- nal bus into one of the input registers under the control of the wr , cs , and dac channel address pins, a0Ca2. the dac outputs are updated on reception of new data into the dac registers. all the outputs may be updated simulta- neously by taking the ldac input low. each dac output is buffered with a gain-of-two amplifier into which an external dac offset voltage can be inserted via the dutgndx pins. the ad7841 is available in a 44-lead mqfp package. rev. b
C2C ad7841?pecifications (v cc = 5 v 5%; v dd = 15 v 10%; v ss = 15 v 10%; gnd = dutgnd = 0 v; r l = 5 k and c l = 50 pf to gnd, t a 1 = t min to t max , unless otherwise noted) parameter a b unit test conditions/comments accuracy resolution 14 14 bits relative accuracy 4 2 lsb max differential nonlinearity C0.9/2 1 lsb max guaranteed monotonic over temperature for all grades zero-scale error 8 8 lsb max v ref (+) = +5 v, v ref (C) = C5 v. typically within 2 lsb full-scale error 8 8 lsb max v ref (+) = +5 v, v ref (C) = C5 v. typically within 2 lsb gain error 2 2 lsb typ v ref (+) = +5 v, v ref (C) = C5 v gain temperature coefficient 2 0.5 0.5 ppm fsr/ c typ 10 10 ppm fsr/ c max dc crosstalk 2 120 120 v max see terminology. typically 75 v reference inputs 2 dc input impedance 100 100 m ? typ input current 1 1 a max per input. typically 0.03 a v ref (+) range 0/5 0/5 v min/max v ref (C) range C5/0 C5/0 v min/max [v ref (+) C v ref (C)] 2/10 2/10 v min/max for specified performance. can go as low as 0 v, but performance not guaranteed dutgnd inputs 2 dc input impedance 60 60 k? typ max input current 0.3 0.3 ma typ per input input range 3 C2/+2 C2/+2 v min/max output characteristics 2 output voltage swing v ss + 2.5 v to v ss + 2.5 v to v typ v out = 2 (v ref (C) + [v ref (+) C v ref (C)] d) v dd C 2.5 v v dd C 2.5 v C v dutgnd short circuit current 15 15 ma max resistive load 5 5 k ? min to 0 v capacitive load 50 50 pf max to 0 v dc output impedance 0.5 0.5 ? max digital inputs 2 v inh , input high voltage 2.4 2.4 v min v inl , input low voltage 0.8 0.8 v max i inh , input current total for all pins @ 25 c 1 1 a max t min to t max 10 10 a max c in , input capacitance 10 10 pf max power requirements 4 v cc 4.75/+5.25 4.75/+5.25 v min/max for specified performance v dd 15 v 10% 15 v 10% v min/max for specified performance v ss C15 v 10% C15 v 10% v min/max for specified performance power supply sensitivity 2 ? full scale/ ? v dd 90 90 db typ ? full scale/ ? v ss 90 90 db typ i cc 0.5 0.5 ma max v inh = v cc , v inl = gnd. dynamic current i dd 10 10 ma max outputs unloaded. typically 8 ma i ss 10 10 ma max outputs unloaded. typically 8 ma notes 1 temperature range for a and b versions: C40 c to +85 c. 2 guaranteed by characterization. not production tested. 3 see dutgnd voltage range section. 4 the ad7841 is functional with power supplies of 12 v 10% with reduced output range. output amplifier requires 2.5 v of head room at the bottom and top ends of the transfer for function. at 12 v supplies it is recommended to restrict the reference range to 4 v. specifications subject to change without notice. rev. b
C3C ad7841 (these characteristics are included for design guidance and are not subject to production testing.) ac performance characteristics a & b parameter versions unit test conditions/comments dynamic performance output voltage settling time 31 s typ full-scale change to 1/2 lsb. dac latch contents alternately loaded with all 0s and all 1s slew rate 0.7 v/ s typ digital-to-analog glitch impulse 230 nv-s typ measured with v ref (+) = +5 v, v ref (C) = C5 v. dac latch alternately loaded with 1fff hex and 2000 hex. not dependent on load conditions channel-to-channel isolation 99 db typ see terminology dac-to-dac crosstalk 40 nv-s typ see terminology digital crosstalk 0.2 nv-s typ feedthrough to dac output under test due to change in digital input code to another converter digital feedthrough 0.1 nv-s typ effect of input bus activity on dac output under test output noise spectral density @ 1 khz 200 nv/ hz typ all 1s loaded to dac. v ref (+) = v ref (C) = 0 v specifications subject to change without notice. timing specifications 1, 2 parameter limit at t min, t max unit description t 1 15 ns min address to wr setup time t 2 0 ns min address to wr hold time t 3 50 ns min cs pulsewidth low t 4 50 ns min wr pulsewidth low t 5 0 ns min cs to wr setup time t 6 0 ns min wr to cs hold time t 7 20 ns min data setup time t 8 0 ns min data hold time t 9 31 s typ settling time t 10 300 ns max clr pulse activation time t 11 50 ns min ldac pulsewidth low notes 1 all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 rise and fall times should be no longer than 50 ns. specifications subject to change without notice. t 1 t 2 t 5 t 6 t 3 t 4 t 7 t 8 t 9 t 10 t 11 ldac clr wr cs a0, a1, a2 data v out v out figure 1. timing diagram (v cc = 5 v 5%; v dd = 15 v 10%; v ss = ?5 v 10%; gnd = dutgnd = 0 v) rev. b
ad7841 C4C absolute maximum ratings 1, 2 (t a = 25 c unless otherwise noted) v cc to gnd 3 . . . . . . . . . . . . . . C0.3 v, +7 v or v dd + 0.3 v (whichever is lower) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +17 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v, C17 v digital inputs to gnd . . . . . . . . . . . . . . C0.3 v, v cc + 0.3 v v ref (+) to v ref (C) . . . . . . . . . . . . . . . . . . . . . C0.3 v, +18 v v ref (+) to gnd . . . . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v v ref (C) to gnd . . . . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v dutgnd to gnd . . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v v out (aCh) to gnd . . . . . . . . . . . . v ss C 0.3 v, v dd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c mqfp package power dissipation . . . . . . . . . . . . . . . . . (t j max C t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 95 c/w notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. 3 v cc must not exceed v dd by more than 0.3 v. if it is possible for this to happen during power supply sequencing, the following diode protection scheme will ensure protection. pin configuration 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41424344 36 35 34 37 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 29 30 31 32 33 27 28 25 26 23 24 dutgnd_gh v out h v ref ()gh v ref (+)gh clr db13 db12 ad7841 dutgnd_ab v out a v ref ()ab v ref (+)ab v dd v ss ldac a2 a1 a0 cs db11 db10 db9 db8 db4 v out b v out c dutgnd_cd v out d v dd v out e dutgnd_ef v out f v out g db7 db5 db6 db2 wr v cc gnd db0 db1 db3 v ref ()cdef v ref (+)cdef v dd v cc ad7841 hp5082-2811 v dd v cc in4148 rev. b
ad7841 C5C pin function descriptions pin no. mnemonic description 1 dutgnd_ab device sense ground for dacs a and b. v out a and v out b are referenced to the voltage applied to this pin. 2, 44, 43, v out a..v out h dac outputs. 41, 37, 35, 34, 32 3, 4 v ref (C)ab, v ref (+)ab reference inputs for dacs a and b. these reference voltages are referred to gnd. 5, 38 v dd positive analog power supply; +15 v 10% for specified performance. 6v ss negative analog power supply; C15 v 10% for specified performance. 7 ldac load dac logic input (active low). when this logic input is taken low the contents of the registers are transferred to their respective dac registers. ldac can be tied permanently low enabling the outputs to be updated on the rising edge of wr . 8, 9, 10 a2, a1, a0 address inputs. a0, a1 and a2 are decoded to select one of the eight input registers for a data transfer. 11 cs level-triggered chip select input (active low). the device is selected when this input is low. 12 wr level-triggered write input (active low), used in conjunction with cs to write data to the ad7841 data registers. data is latched into the selected input register on the rising edge of wr . 13 v cc logic power supply; 5 v 5%. 14 gnd ground. 15C28 db 0 . . db12 parallel data inputs. the ad7841 can accept a straight 14-bit parallel word on db0 to db13 where db13 is the msb and db0 is the lsb. 29 clr asynchronous clear input (level sensitive, active low). when this input is low, all analog outputs are switched to the externally set potential on the relevant dutgnd pin. the con- tents of input registers and dac registers a to h are not affected when the clr pin is taken low. when clr is brought back high, the dac outputs revert to their original outputs as determined by the data in their dac registers. 30, 31 v ref (+)gh, v ref (C)gh reference inputs for dacs g and h. these reference voltages are referred to gnd. 33 dutgnd_gh device sense ground for dacs g and h. v out g and v out h are referenced to the voltage applied to this pin. 36 dutgnd_ef device sense ground for dacs e and f. v out e and v out f are referenced to the voltage applied to this pin. 39 v ref (+)cdef reference inputs for dacs c, d, e and f. these reference voltages are referred to gnd. 40 v ref (C)cdef reference inputs for dacs c, d, e and f. these reference voltages are referred to gnd. 42 dutgnd_cd device sense ground for dacs c and d. v out c and v out d are referenced to the voltage applied to this pin. rev. b
ad7841 C6C terminology relative accuracy relative accuracy or endpoint linearity is a measure of the max- imum deviation from a straight line passing through the end points of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. dc crosstalk although the common input reference voltage signals are inter- nally buffered, small ir drops in the individual dac reference inputs across the die can mean that an update to one channel can produce a dc output change in one or another of the chan- nel outputs. the eight dac outputs are buffered by op amps that share common v dd and v ss power supplies. if the dc load cur rent changes in one channel (due to an update), this can result in a further dc change in one or another of the channel outputs. this effect is most obvious at high load currents and reduces as the load currents are reduced. with high impedance loads the effect is virtually impossible to measure. output voltage settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is specified as the area of the glitch in nv-secs. it is measured with v ref (+) = +5 v and v ref (C) = C5 v and the digital i nputs toggled between 1fffh and 2000h. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dacs reference input that appears at the out- put of another dac. it is expressed in dbs. dac-to-dac crosstalk dac-to-dac crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog o/p change at another converter. it is specified in nv-secs. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nv-secs. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the v out pins. this noise is digital feedthrough. dc output impedance this is the effective output source resistance. it is dominated by package lead resistance. full-scale error this is the error in dac output voltage when all 1s are loaded into the dac latch. ideally the output voltage, with all 1s loaded into the dac latch, should be 2 v ref (+) C 1 lsb. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac latch. ideally the output voltage, with all 0s in the dac latch should be equal to 2 v ref (C). zero- scale error is mainly due to offsets in the output amplifier. gain error gain error is defined as (full-scale error) C (zero-scale error). general description dac architecturegeneral each channel consists of a straight 14-bit r-2r voltage-mode dac. the full-scale output voltage range is equal to twice the reference span of v ref (+) C v ref (C). the dac coding is straight binary; all 0s produces an output of 2 v ref (C); all 1s produces an output of 2 v ref (+) C 1 lsb. the analog output voltage of each dac channel reflects the contents of its own dac register. data is transferred from the external bus to the input register of each dac on a per channel basis. bringing the clr line low switches all the signal outputs, v out a to v out h, to the voltage level on the relevant dutgnd pin. when the clr signal is brought back high, the output voltages from the dacs will reflect the data stored in the relevant dac registers. data loading to the ad7841 data is loaded into the ad7841 in straight parallel 14-bit wide words. the dac output voltages, v out a C v out h are updated to reflect new data in the dac registers. the actual input register being written to is determined by the logic levels present on the devices address lines, as shown in table i. table i. address line truth table a2 a1 a0 dac selected 0 0 0 input reg a (dac a) 0 0 1 input reg b (dac b) 0 1 0 input reg c (dac c) 0 1 1 input reg d (dac d) 1 0 0 input reg e (dac e) 1 0 1 input reg f (dac f) 1 1 0 input reg g (dac g) 1 1 1 input reg h (dac h) rev. b
ad7841 C7C typical performance characteristics inl error lsbs code 2 2 0 2048 1 0 4096 12288 16384 1 6144 8192 10240 14336 v dd = +15v v ss = 15v v ref (+) = +5v v ref () = 5v t a = 25c tpc 1. typical inl plot dnl error lsbs 1 1 0.5 0.5 0 temperature c 40 100 200 20406080 v dd = +15v v ss = 15v v ref (+) = +5v v ref (+) = 5v tpc 4. typical dnl error vs. temperature 0.6 0.5 0.4 0.3 0.1 volts 0.2 0 0.1 0.2 0 500 1 000 1 500 2 000 2 500 3000 3500 4 000 4 500 5000 tpc 7. typical digital-to-analog glitch impulse code 1 1 0 2048 0.75 0.25 0 0.5 4096 6144 8192 dnl error lsbs 0.25 0.5 0.75 10240 12288 14336 16384 v dd = +15v v ss = 15v v ref (+) = +5v v ref () = 5v t a = 25c tpc 2. typical dnl plot error lsbs temperature c 4 2 4 0 2 40 20 100 0 20406080 v dd = +15v v ss = 15v v ref(+) = +5v v ref( ) = 5v full-scale error zero-scale error tpc 5. zero-scale and full-scale error vs. temperature v out volts 10.19 10.17 10.16 10.18 settling time s 27 33 28 29 30 31 32 tpc 8. settling time (+) inl error lsbs temperature c 4 2 1 0 2 40 20 100 0 20406080 v dd = +15v v ss = 15v v ref (+) = +5v v ref ( ) = 5v tpc 3. typical inl error vs. temperature temperature c 40 100 200 20406080 6 1 i cc ma 1 5 3 4 2 0 v cc = +5v v dd = +15v v ss = 15v digital inputs @ supplies digital inputs @ thresholds tpc 6. i cc vs. temperature 10 8 6 4 40 20 0 20 40 60 i dd /i ss ma temperature c 80 100 i ss i dd v dd = +15v v ss = 15v v cc = +5v tpc 9. i dd , i ss vs. temperature rev. b
ad7841 C8C unipolar configuration figure 2 shows the ad7841 in the unipolar binary circuit configuration. the v ref (+) input of the dac is driven by the ad586, a 5 v reference. v ref (C) is tied to ground. table ii gives the code table for unipolar operation of the ad7841. other suitable references include the ref02, a precision 5 v reference, and the ref195, a low dropout, micropower preci- sion 5 v reference. ad7841* v dd v cc v ref (+) v out dutgnd gnd v ss v ref () signal gnd 15v v out (0 to +10v) +5v +15v ad586 r1 10k 2 6 5 4 8 c1 1f signal gnd *additional pins omitted for clarity figure 2. unipolar 10 v operation offset and gain may be adjusted in figure 2 as follows: to adjust offset, disconnect the v ref (C) input from 0 v, load the dac with all 0s and adjust the v ref (C) voltage u ntil v out = 0 v. for gain adjustment, the ad7841 should be loaded with all 1s and r1 adjusted until v out = 2 v ref (+) C 1 lsb = 10 v(16383/ 16384) = 9.99939 v. many circuits will not require these offset and gain adjustments. in these circuits r1 can be omitted. pin 5 of the ad586 may be left open circuit and pin 2 (v ref (C)) of the ad7841 tied to 0 v. table ii. code table for unipolar operation binary number in dac register analog output msb lsb (v out ) 11 1111 1111 1111 2 v ref (16383/16384) v 10 0000 0000 0000 2 v ref (8192/ 16384) v 01 1111 1111 1111 2 v ref (8191/ 16384) v 00 0000 0000 0001 2 v ref (1/16384) v 00 0000 0000 0000 0 v notes v= v ref (+); v ref (C) = 0 v for unipolar operation. for v ref (+) = 5 v, 1 lsb = 10 v/2 14 = 10 v/16384 = 610 v. bipolar configuration figure 3 shows the ad7841 set up for 10 v operation. the ad588 provides precision 5 v tracking outputs that are fed to the v ref (+) and v ref (C) inputs of the ad7841. the code table for bipolar operation of the ad7841 is shown in table iii. in figure 3, full-scale and bipolar zero adjustments are provided by varying the gain and balance on the ad588. r2 varies the gain on the ad588 while r3 adjusts the offset of both the +5 v and C5 v outputs together with respect to ground. for bipolar-zero adjustment, the dac is loaded with 1000... 0000 and r3 is adjusted until v out = 0 v. full scale is adjusted by loading the dac with all 1s and adjusting r2 until v out = 10(8191/8192) v = 9.99878 v. when bipolar-zero and full-scale adjustment are not needed, r2 and r3 can be omitted. pin 12 on the ad588 should be con- nected to pin 11 and pin 5 should be left floating. ad7841* v dd v cc v ref (+) v out dutgnd gnd v ss v ref () signal gnd 15v v out (10v to +10v) +5v +15v *additional pins omitted for clarity r1 39k c1 1 f r2 100k r3 100k ad588 46 2 3 1 14 15 16 7 9 5 10 11 12 8 13 figure 3. bipolar 10 v operation table iii. code table for bipolar operation binary number in dac register analog output msb lsb (v out ) 11 1111 1111 1111 2[v ref (C) + v ref (16383/16384)] v 10 0000 0000 0001 2[v ref (C) + v ref (8193/16384)] v 10 0000 0000 0000 2[v ref (C) + v ref (8192/16384)] v 01 1111 1111 1111 2[v ref (C) + v ref (8191/16384)] v 00 0000 0000 0001 2[v ref (C) + v ref (1/16384)] v 00 0000 0000 0000 2[v ref (C)] v notes v ref = (v ref (+) C v ref (C)). for v ref (+) = +5 v, and v ref (C) = C5 v, v ref = 10 v, 1 lsb = 2 v ref v/2 14 = 20 v/16384 = 1.22 mv. controlled power-on of the output stage a block diagram of the output stage of the ad7841 is shown in figure 4. it is capable of driving a load of 5 k ? in parallel with 50 pf. g 1 to g 6 are transmission gates used to control the power on voltage present at v out . on power up g 1 and g 2 are also used in conjunction with the clr input to set v out to the user defined voltage present at the dutgnd pin. when clr is taken back high, the dac outputs reflect the data in the dac registers. g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r = 60k 14k dac figure 4. block diagram of ad7841 output stage rev. b
ad7841 C9C power-on with clr low the output stage of the ad7841 has been designed to allow output stability during power-on. if clr is kept low during power-on, then just after power is applied to the ad7841, the situation is as depicted in figure 5. g 1 , g 4 and g 6 are open while g 2 , g 3 and g 5 are closed. g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r 14k dac figure 5. output stage with v dd < 7 v or v ss > C3 v; clr low v out is kept within a few hundred millivolts of dutgnd via g 5 and a 14 k ? resistor. this thin-film resistor is connected in parallel with the gain resistors of the output amplifier. the output amplifier is connected as a unity gain buffer via g 3 , and the dutgnd voltage is applied to the buffer input via g 2 . the amplifiers output is thus at the same voltage as the dutgnd pin. the output stage remains configured as in figure 5 until the voltage at v dd exceeds 7 v and v ss is more negative than C3 v. by now the output amplifier has enough headroom to handle signals at its input and has also had time to settle. the internal power-on circuitry opens g 3 and g 5 and closes g 4 and g 6 . this situation is shown in figure 6. now the output ampli- fier is configured in its noise gain configuration via g 4 and g 6 . the dutgnd voltage is still connected to the noninverting input via g 2 and this voltage appears at v out . g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r 14k dac figure 6. output stage with v dd > 7 v and v ss < C3 v; clr low v out has been disconnected from the dut gnd pin by the opening of g 5 , but will track the voltage present at dutgnd via the configuration shown in figure 6. when clr is taken back high, the output stage is configured as shown in figure 7. the internal control logic closes g 1 and opens g 2 . the output amr})fier is connected in a noninverting gain-of-two configuration. the voltage that appears on the v out pins is determined by the data present in the dac registers. g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r 14k dac figure 7. output stage after clr is taken high power-on with clr high if clr is high on the application of power to the device, the output stages of the ad7841 are configured as in figure 8 w hile v dd is less than 7 v and v ss is more positive than C3 v. g 1 is closed and g 2 is open, thereby connecting the output of the dac to the input of its output amplifier. g 3 and g 5 are closed while g 4 and g 6 are open, thus connecting the output amplifier as a unity gain buffer. v out is connected to dutgnd via g 5 through a 14 k ? resistor until v dd exceeds 7 v and v ss is more negative than C3 v. g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r 14k dac figure 8. output stage powering up with clr high while v dd < 7 v or v ss > C3 v when the difference between the supply voltages reaches 10 v, the internal power-on circuitry opens g 3 and g 5 and closes g 4 and g 6 configuring the output stage as shown in figure 9. g 1 g 2 g 4 g 3 g 6 g 5 dutgnd v out r r 14k dac figure 9. output stage powering up with clr high when v dd > 7 v and v ss < C3 v rev. b
ad7841 C10C dutgnd voltage range during power-on, the v out pins of the ad7841 are connected to the relevant dutgnd pins via g 5 and the 14 k ? thin-film resistor. the dutgnd potential must obey the max ratings at all times. thus, the voltage at dutgnd must always be within the range v ss C 0.3 v, v dd + 0.3 v. however, in order that the voltages at the v out pins of the ad7841 stay within 2 v of the relevant dutgnd potential during power-on, the voltage applied to dutgnd should also be kept within the range gnd C 2 v, gnd + 2 v. once the ad7841 has powered on and the on-chip amplifiers have settled, any voltage that is now applied to the dutgnd pin is subtracted from the dac output, which has been gained up by a factor of two. thus, for specified operation, the maximum voltage that can be applied to the dutgnd pin increases to the maximum allowable 2 v ref (+) voltage, and the minimum volt- age that can be applied to dutgnd is the minimum 2 v ref (C) voltage. after the ad7841 has fully powered on, the outputs can track any dutgnd voltage within this minimum/maxi- mum range. power supply sequencing when operating the ad7841, it is important that ground be connected at all times to avoid high current states. the recom- mended power-up sequence is v dd /v ss followed by v cc . if v cc can exceed v dd on power-up, the diode scheme shown in the absolute maximum ratings section will ensure protection. the reference inputs and digital inputs should be powered up last. should the references exceed v dd /v ss on power-up, current limiting resistors should be inserted in series with the reference inputs to limit the current to 20 ma. logic inputs should not be applied before v cc . current limiting resistors (470 ? ) in series with the logic inputs should be inserted if these inputs come up before v cc . microprocessor interfacing interfacing the ad784116-bit interface the ad7841 can be interfaced to a variety of 16-bit micro- controllers or dsp processors. figure 10 shows the ad7841 interfaced to a generic 16-bit microcontroller/dsp processor. the lower address lines from the processor are connected to a0, a1 and a2 on the ad7841 as shown. the upper address lines are decoded to provide a chip select signal or an ldac signal for the ad7841. the fast interface timing of the ad7841 allows direct interface to a wide variety of microcontrollers and dsps as shown in figure 10. ad7841 controller/ dsp processor* address decode d13 d0 data bus upper bits of address bus a2 a1 a0 r/w *additional pins omitted for clarity d13 d0 cs ldac a2 a1 a0 wr figure 10. parallel interface applications power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad7841 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and ana- log ground planes should be joined at only one place. the gnd pin of the ad7841 should be connected to the agnd of the system. if the ad7841 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only, a star ground point that should be established as close as possible to the ad7841. digital lines running under the device should be avoided as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7841 to avoid noise coupling. the power supply lines of the ad7841 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is by far the best but not always possible with a double sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. rev. b
ad7841 C11C the ad7841 should have ample supply bypassing located as close to the package as possible, ideally right up against the device. figure 11 shows the recommended capacitor values of 10 f in parallel with 0.1 f on each of the supplies. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequen- cies to handle transient currents due to internal logic switching. 10f 0.1f1 0 f 0.1f 10f 0.1f v cc v dd v ss ad7841 figure 11. reco mmended decoupling scheme for ad7841 automated test equipment the ad7841 is particularly suited for use in an automated test environment. figure 12 shows the ad7841 providing the neces- sary voltages for the pin driver and the window comparator in a typical ate pin electronics configuration. ad588s are used to provide reference voltages for the ad7841. in the configuration shown, the ad588s are configured so that the voltage at pin 1 is 5 v greater than the voltage at pin 9 and the voltage at pin 15 is 5 v less than the voltage at pin 9. ad7841* v ref (+)ab v out b dutgnd_gh v out g v out h gnd dutgnd_ab *additional pins omitted for clarity v out a v ref ()ab v ref (+)gh v ref ()gh to tester window comparator v out device gnd device gnd 15v +15v pin driver ad588 0.1f v offset +15v 15v 4 6 8 13 2 16 3 1 15 14 9 ad588 +15v 15v 4 6 9 13 7 2 16 3 1 15 14 8 10 11 12 1f device gnd 10 11 12 7 1f figure 12. ate application one of the ad588s is used as a reference for dacs a and b. these dacs are used to provide high and low levels for the pin driver. the pin driver may have an associated offset. this can be nulled by applying an offset voltage to pin 9 of the ad588. first, the code 100 0...0000 is loaded into the daca latch and the pin driver output is set to the daca output. the v offset voltage is adjusted until 0 v appears between the pin driver output and dutgnd. this causes both v ref (+) and v ref (C) to be offset with respect to gnd by an amount equal to v offset . however, the output of the pin driver will vary from C10 v to +10 v with respect to dutgnd as the dac input code varies from 00 0...000 to 111...111. the v offset voltage is also applied to the dutgnd pins. when a clear is performed on the ad7841, the output of the pin driver will be 0 v with respect to dutgnd. the other ad588 is used to provide a reference voltage for dacs g and h. these provide the reference voltages for the window comparator shown in the diagram. note that pin 9 of this ad588 is connected to device gnd. this causes v ref (+)gh and v ref (C)gh to be referenced to device gnd. as dac g and dac h input codes vary from 00 0...000 to 111...111, v out g and v out h vary from C10 v to +10 v with respect to device gnd. device gnd is also connected to dutgnd. when the ad7841 is cleared, v out g and v out h are cleared to 0 v with respect to device gnd. programmable reference generation for the ad7841 in an ate application the ad7841 is particularly suited for use in an automated test environment. the reference input for the ad7841 octal 14-bit dac requires three differential references for the eight dacs. programmable references may be a requirement in some ate applications as the offset and gain errors at the output of a dac can be adjusted by varying the voltages on the reference pins of the dac. to trim offset errors, the dac is loaded with the digital code 000...000 and the voltage on the v ref (C) pin is adjusted until the desired negative output voltage is obtained. to trim out gain errors, first the offset error is trimmed. then the dac is loaded with the code 11 1...111 and the voltage on the v ref (+) pin is adjusted until the desired full-scale voltage minus one lsb is obtained. it is not uncommon in ate design, to have other circuitry at the output of the ad7841 that can have offset and gain errors of up to say 300 mv. these offset and gain errors can be easily removed by adjusting the reference voltages of the ad7841. the ad7841 uses nominal reference values of 5 v to achieve an output span of 10 v. since the ad7841 has a gain of two from the reference inputs to the dac output, adjusting the reference voltages by 150 mv will adjust the dac offset and gain by 300 mv. there are a number of suitable 8- and 10-bit dacs available that would be suitable to drive the reference inputs of the ad7841, such as the ad7804, a quad 10-bit digital-to-analog converter with serial load capabilities. the voltage output from this dac is in the form of v bias v swing and rail-to-rail operation is achievable. the voltage reference for this dac can be inter- nally generated or provided externally. this dac also contains an 8-bit sub dac which can be used to shift the complete trans- fer function of each dac around the v bias point. this can be used as a fine trim on the output voltage. in this application two ad7804s are required to provide programmable reference capabil- ity for all eight dacs. one ad7804 is used to drive the v ref (+) pins and the second package used to drive the v ref (C) pins. another suitable dac for providing programmable reference capability is the ad8803. this is an octal 8-bit trimdac ? and provides independent control of both the top and bottom ends of the trimdac. this is helpful in maximizing the reso- lution of devices with a limited allowable voltage control range. trimdac is a registered trademark of analog devices, inc. rev. b
ad7841 C12C gnd v dd 8/10-bit dac gnd v dd 8/10-bit dac logic level shift +5v 5v sclk d in fsin/cs sclk d in fsin/cs 0v to +5v 0v to 5v v ref (+)ab a0, a1, a2 v out a v out a v out b v out b v ref ()ab ad7841* gnd data bus addr decoder addr bus sdata sclk data bus controller *additional pins omitted for clarity figure 13. programmable reference generation for the ad7841 the ad8803 has an output voltage range of gnd to v dd (0 v to 5 v). to trim the v ref (+) input, the appropriate trim range on the ad8803 dac can be set using the v refl and v refh pins allowing 8 bits of resolution between the two points. this will allow the v ref (+) pin to be adjusted to remove gain errors. to trim the v ref (C) voltage, some method of providing a trim voltage in the required negative voltage range is required. neither the ad7804 or the ad8803 can provide this range in normal operation as their output range is 0 v to 5 v. there are two methods of producing this negative voltage. one method is to provide a positive output voltage and then to level shift that ana- log voltage to the required negative range. alternatively these dacs can be operated with supplies of 0 v and C5 v, with the v dd pin connected to 0 v and the gnd pin connected to C5 v. now these can be used to provide the negative reference volt- ages for the v ref (C) inputs on the ad7841. however, the digital signals driving the dacs need to be level-shifted from the 0 v to +5 v range to the C5 v to 0 v range. figure 13 shows a typical application circuit to provide programmable reference capabilities for the ad7841. rev. b
ad7841 rev. b | page 1 3 of 1 3 outline dimensions compliant to jedec standards mo-112-aa-1 041807-a 14.15 13.90 sq 13.65 0.45 0.30 2.45 max 1.03 0.88 0.73 top view (pins down) 12 44 1 22 23 34 33 11 0.25 min 2.20 2.00 1.80 7 0 view a rotated 90 ccw 0.23 0.11 10.20 10.00 sq 9.80 0.80 bsc lead pitch lead width 0.10 coplanarity v i e w a s e a t i n g p l a n e 1 . 9 5 r e f pin 1 figure 14. 44-lead metric quad flat package [mqfp] (s-44-2) dimensions shown in millimeters ordering guide model 1 linearity error (lsbs) dnl (lsbs) te mperature range package description package option ad7841asz 4 ?0.9/+2 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 AD7841ASZ-REEL 4 ?0.9/+2 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 ad7841bsz 2 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 ad7841bsz-reel 2 1 ?40c to +85c 44-lead metric quad flat package [mqfp] s-44-2 eval-ad7841ebz evaluation board 1 z = rohs compliant part. revision history 1/11rev. a to rev. b changes to absolute maximum ratings, lead temperature ...... 4 updated outline dimensions ........................................................ 13 moved and changes to ordering guide ...................................... 13 ?1999-2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09645-0-1/11(b)

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